In the semiconductor manufacturing processes, it is most difficult to make contact at the specific location and to form good contact holes without damaging the substrate layer during etching process. This is due to the ever-increasing scale of integration of circuits thus demanding that the thickness of oxide gate layers and misalign margin of the contact formation be reduced further. Hence, there is a need for soft-landing etching methods for gate etching and contact hole etching in order to prevent gate oxide damage or field oxide damage during etching process.
Underneath all the layers fabricated upon the semiconductor substrate is the basic structure of and active and/or field oxide areas laid down according to the previous patterning process of semiconductor fabrication. It is a demanding and exacting process in a gate or contact formation to etch the contact hole without or with insignificant field oxide loss on the previous layer.
The soft-landing etching process endeavours to overcome this problem. The prior art technology was to use oxinitride film to prevent gate oxide or field oxide from being over-etched during poly gate etching or contact hole etching process.
In addition to preventing over-etching, the contact area of a contact hole must not be affected by its side wall taper, hence a high degree of anisotropic etching is also required and which is assuaged by, for example, high-density plasma etching techniques so that the side wall oxide or nitride may be protected during the contact hole etching process.
In U.S. Pat. No. 5,948,703 (Shen) the soft-landing gate etching comprises laying specific layers of materials and using a series of 3 different etchants, each being specific to the materials to be etched. This includes forming a polysilicon layer on the oxide layer, forming a layer of conductive material on the polysilicon layer and forming a mask defining the elements of the semiconductor device. The first etching step substantially removes the entire conductive layer through the mask (with a high density plasma) between the elements. The second etching step removes the polysilicon until the oxide layer is exposed between the elements. A third etching step then removes the polysilicon residues from the oxide layer between the elements.
This prior art technique may be especially difficult to apply without using additional layer such as nitride or oxinitride when a contact hole falls on the boundary between an active area and a field oxide. A misalignment or over-etching can cause the loss of the field silicon oxide layer during etching process and this loss of the silicon oxide may cause leakage in the circuit during the operation of the semiconductor device.